An experiment on DES statistical cryptanalysis
CCS '96 Proceedings of the 3rd ACM conference on Computer and communications security
Side Channel Cryptanalysis of Product Ciphers
ESORICS '98 Proceedings of the 5th European Symposium on Research in Computer Security
A Practical Implementation of the Timing Attack
CARDIS '98 Proceedings of the The International Conference on Smart Card Research and Applications
Differential Fault Analysis of Secret Key Cryptosystems
CRYPTO '97 Proceedings of the 17th Annual International Cryptology Conference on Advances in Cryptology
Low Cost Attacks on Tamper Resistant Devices
Proceedings of the 5th International Workshop on Security Protocols
Crypto in Europe - Markets, Law and Policy
Proceedings of the International Conference on Cryptography: Policy and Algorithms
FSE '97 Proceedings of the 4th International Workshop on Fast Software Encryption
VINCI: Secure Test of a VLSI High-Speed Encryption System
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Selecting Cryptographic Key Sizes
PKC '00 Proceedings of the Third International Workshop on Practice and Theory in Public Key Cryptography: Public Key Cryptography
Concurrent Error Detection in Block Ciphers
ITC '00 Proceedings of the 2000 IEEE International Test Conference
On the importance of checking cryptographic protocols for faults
EUROCRYPT'97 Proceedings of the 16th annual international conference on Theory and application of cryptographic techniques
On the implementation of the advanced encryption standard on a public-key crypto-coprocessor
CARDIS'02 Proceedings of the 5th conference on Smart Card Research and Advanced Application Conference - Volume 5
An EDA tool for implementation of low power and secure crypto-chips
Computers and Electrical Engineering
A fault-tolerant pipelined architecture for symmetric block ciphers
Computers and Electrical Engineering
Coding Schemes for Arithmetic and Logic Operations - How Robust Are They?
Information Security Applications
A compact AES core with on-line error-detection for FPGA applications with modest hardware resources
Microprocessors & Microsystems
Side channel cryptanalysis on SEED
WISA'04 Proceedings of the 5th international conference on Information Security Applications
A Comparative Survey on Cryptology-Based Methodologies
International Journal of Information Security and Privacy
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Fault-based side channel cryptanalysis is very effective against symmetric and asymmetric encryption algorithms. Although straightforward hardware and time redundancy based concurrent error detection (CED) architectures can be used to thwart such attacks, they entail significant overhead (either area or performance). In this paper we investigate systematic approaches to low-cost, low-latency CED for symmetric encryption algorithms based on the inverse relationship that exists between encryption and decryption at algorithm level, round level and operation level and develop CED architectures that explore the trade-off between area overhead, performance penalty and error detection latency. The proposed techniques have been validated on FPGA implementations of AES finalist 128-bit symmetric encryption algorithms.