Proceedings of the 38th annual Design Automation Conference
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
VINCI: Secure Test of a VLSI High-Speed Encryption System
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Concurrent Error Detection in Block Ciphers
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Wafer-scale integration of systolic arrays
SFCS '82 Proceedings of the 23rd Annual Symposium on Foundations of Computer Science
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Secure transmission over wired/wireless networks requires encryption of data and control information. For high-speed data transmission, it would be desirable to implement the encryption algorithms in hardware. Faults in the hardware, however, may cause interruption of service. This paper presents a simple technique for achieving fault tolerance in pipelined implementation of symmetric block ciphers. It detects errors, locates the corresponding faults, and readily reconfigures during normal operation to isolate the identified faulty modules. Bypass links with some extra pipeline stages are used to achieve fault tolerance. The hardware overhead can be controlled by properly choosing the number of extra stages. Moreover, fault tolerance is achieved with negligible time overhead.