Threshold implementations of all 3×3 and 4×4 s-boxes

Authors:
Begül Bilgin;Svetla Nikova;Ventzislav Nikov;Vincent Rijmen;Georg Stütz
Affiliations:
Dept. ESAT/SCD-COSIC and IBBT, KU Leuven, Belgium,EEMCS-DIES, University of Twente, The Netherlands;Dept. ESAT/SCD-COSIC and IBBT, KU Leuven, Belgium;NXP Semiconductors, Belgium;Dept. ESAT/SCD-COSIC and IBBT, KU Leuven, Belgium,IAIK, Graz University of Technology, Austria;IAIK, Graz University of Technology, Austria
Venue:
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
Year:
2012

Citing 23
Cited 4

A New Approach to Block Cipher Design

Fast Software Encryption, Cambridge Security Workshop
Bitslice Ciphers and Power Analysis Attacks

FSE '00 Proceedings of the 7th International Workshop on Fast Software Encryption
The Round Functions of RIJNDAEL Generate the Alternating Group

FSE '02 Revised Papers from the 9th International Workshop on Fast Software Encryption
An Implementation of DES and AES, Secure against Some Attacks

CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Multiplicative Masking and Power Analysis of AES

CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation

Proceedings of the conference on Design, automation and test in Europe - Volume 1
On the Classification of 4 Bit S-Boxes

WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Using Normal Bases for Compact Hardware Implementations of the AES S-Box

SCN '08 Proceedings of the 6th international conference on Security and Cryptography for Networks
Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches

Information Security and Cryptology --- ICISC 2008
PRINTcipher: a block cipher for IC-printing

CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Provably secure higher-order masking of AES

CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches

Journal of Cryptology - Special Issue on Hardware and Security
Side-Channel Resistant Crypto for Less than 2,300 GE

Journal of Cryptology - Special Issue on Hardware and Security
Pushing the limits: a very compact and a threshold implementation of AES

EUROCRYPT'11 Proceedings of the 30th Annual international conference on Theory and applications of cryptographic techniques: advances in cryptology
Higher-order glitches free implementation of the AES using secure multi-party computation protocols

CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
On the power of fault sensitivity analysis and collision side-channel attacks in a combined setting

CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Provably secure masking of AES

SAC'04 Proceedings of the 11th international conference on Selected Areas in Cryptography
Threshold implementations against side-channel attacks and glitches

ICICS'06 Proceedings of the 8th international conference on Information and Communications Security
A side-channel analysis resistant description of the AES s-box

FSE'05 Proceedings of the 12th international conference on Fast Software Encryption
Small size, low power, side channel-immune AES coprocessor: design and synthesis results

AES'04 Proceedings of the 4th international conference on Advanced Encryption Standard
Successfully attacking masked AES hardware implementations

CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints

CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Cryptographic analysis of all 4 × 4-bit s-boxes

SAC'11 Proceedings of the 18th international conference on Selected Areas in Cryptography

On 3-share threshold implementations for 4-bit s-boxes

COSADE'13 Proceedings of the 4th international conference on Constructive Side-Channel Analysis and Secure Design
On the simplicity of converting leakages from multivariate to univariate: case study of a glitch-resistant masking scheme

CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
FIDES: lightweight authenticated cipher with side-channel resistance for constrained hardware

CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
Improbable differential attacks on Present using undisturbed bits

Journal of Computational and Applied Mathematics

Quantified Score

Hi-index	0.00

Visualization

Abstract

Side-channel attacks have proven many hardware implementations of cryptographic algorithms to be vulnerable. A recently proposed masking method, based on secret sharing and multi-party computation methods, introduces a set of sufficient requirements for implementations to be provably resistant against first-order DPA with minimal assumptions on the hardware. The original paper doesn't describe how to construct the Boolean functions that are to be used in the implementation. In this paper, we derive the functions for all invertible 3 ×3, 4 ×4 S-boxes and the 6 ×4 DES S-boxes. Our methods and observations can also be used to accelerate the search for sharings of larger (e.g. 8 ×8) S-boxes. Finally, we investigate the cost of such protection.