A novel circuit design methodology to reduce side channel leakage

Authors:
Andreas Gornik;Ivan Stoychev;Jürgen Oehm
Affiliations:
Analogue Integrated Circuits Research Group, Ruhr-Universität Bochum, Bochum, Germany;Analogue Integrated Circuits Research Group, Ruhr-Universität Bochum, Bochum, Germany;Analogue Integrated Circuits Research Group, Ruhr-Universität Bochum, Bochum, Germany
Venue:
SPACE'12 Proceedings of the Second international conference on Security, Privacy, and Applied Cryptography Engineering
Year:
2012

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Abstract

To estimate the probable information leakage of a logic circuit through a side channel is a major problem for circuit designers. In this paper a novel circuit design methodology is presented to estimate and reduce the side channel leakage of logic gates. The focus lies on the investigation of side channel leakage during circuit design. With this novel methodology three different logic circuit families are compared. Additionally, the process of improving a logic circuit using this methodology is shown in detail.