IC Failure Analysis: Magic, Mystery, and Science
IEEE Design & Test
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients
Journal of Electronic Testing: Theory and Applications
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Trojan Detection using IC Fingerprinting
SP '07 Proceedings of the 2007 IEEE Symposium on Security and Privacy
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
Designing and implementing malicious hardware
LEET'08 Proceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats
Power supply signal calibration techniques for improving detection resolution to hardware Trojans
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Detecting malicious inclusions in secure hardware: Challenges and solutions
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
A region based approach for the identification of hardware Trojans
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
On-demand transparency for improving hardware Trojan detectability
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Hardware Trojan detection using path delay fingerprint
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Extended abstract: Designer's hardware Trojan horse
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Analysis and mitigation of process variation impacts on Power-Attack Tolerance
Proceedings of the 46th Annual Design Automation Conference
Experiences in Hardware Trojan design and implementation
HST '09 Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust
IEEE Spectrum
Hardware trojans for inducing or amplifying side-channel leakage of cryptographic software
INTRUST'10 Proceedings of the Second international conference on Trusted Systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Hardware trojan resistant computation using heterogeneous COTS processors
ACSC '13 Proceedings of the Thirty-Sixth Australasian Computer Science Conference - Volume 135
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Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circuit foundries to covertly implant malicious hardware Trojans into a genuine design. Hardware Trojans provide back doors for on-chip manipulation, or leak secret information off-chip once the compromised IC is deployed in the field. This paper explores the design space of hardware Trojans and proposes a novel technique, "Malicious Off-chip Leakage Enabled by Side-channels" (MOLES), which employs power side-channels to convey secret information off-chip. An experimental MOLES circuit is designed with fewer than 50 gates and is embedded into an Advanced Encryption Standard (AES) cryptographic circuit in a predictive 45nm CMOS technology model. Engineered by a spread-spectrum technique, the MOLES technique is capable of leaking multi-bit information below the noise power level of the host IC to evade evaluators' detections. In addition, a generalized methodology for a class of MOLES circuits and design verification by statistical correlation analysis are presented. The goal of this work is to demonstrate the potential threats of MOLES on embedded system security. Nevertheless, MOLES could be constructively used for hardware authentication, fingerprinting and IP protection.