SWIFT: Software Implemented Fault Tolerance
Proceedings of the international symposium on Code generation and optimization
Designing and implementing malicious hardware
LEET'08 Proceedings of the 1st Usenix Workshop on Large-Scale Exploits and Emergent Threats
Integrated circuit security: new threats and solutions
Proceedings of the 5th Annual Workshop on Cyber Security and Information Intelligence Research: Cyber Security and Information Intelligence Challenges and Strategies
Trojan Side-Channels: Lightweight Hardware Trojans through Side-Channel Engineering
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Experiences in Hardware Trojan design and implementation
HST '09 Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust
MOLES: malicious off-chip leakage enabled by side-channels
Proceedings of the 2009 International Conference on Computer-Aided Design
Preventing IC Piracy Using Reconfigurable Logic Barriers
IEEE Design & Test
MB-LITE: a robust, light-weight soft-core implementation of the MicroBlaze architecture
Proceedings of the Conference on Design, Automation and Test in Europe
Trustworthy computing in a multi-core system using distributed scheduling
IOLTS '10 Proceedings of the 2010 IEEE 16th International On-Line Testing Symposium
A case study in hardware Trojan design and implementation
International Journal of Information Security
SP '11 Proceedings of the 2011 IEEE Symposium on Security and Privacy
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Hardware Trojans pose a credible and increasing threat to computer security, with the potential to compromise the very electronics that ostensibly provide the security primitives underpinning various computer architectures. The discovery of stealthy Hardware Trojans within Integrated Circuits by current state-of-the-art pre-and post-manufacturing test and verification techniques cannot be guaranteed. Therefore electronic systems, especially those controlling safety or security critical systems should be designed to operate with integrity in the presence of any Hardware Trojans, and regardless of any Trojan activity. We present an architecture that fragments and replicates computation over a pool of Commercial-Off-The-Shelf processors with widely heterogeneous architectures. Processors are loosely synchronised through their use of a voted, architecture-independent message box mechanism to access a common memory space. A minimal Trusted Computing Base abstracts the processors as a single computational entity that can tolerate the effects of arbitrary Hardware Trojans within individual processors. The architecture provides integrity, data confidentiality, and availability for executing applications.