Garbled circuits for leakage-resilience: hardware implementation and evaluation of one-time programs

  • Authors:
  • Kimmo Järvinen;Vladimir Kolesnikov;Ahmad-Reza Sadeghi;Thomas Schneider

  • Affiliations:
  • Dep. of Information and Comp. Science, Aalto University, Finland;Alcatel-Lucent Bell Laboratories, Murray Hill, NJ;Horst Görtz Institute for IT-Security, Ruhr-University Bochum, Germany;Horst Görtz Institute for IT-Security, Ruhr-University Bochum, Germany

  • Venue:
  • CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
  • Year:
  • 2010

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Abstract

The power of side-channel leakage attacks on cryptographic implementations is evident. Today's practical defenses are typically attack-specific countermeasures against certain classes of side-channel attacks. The demand for a more general solution has given rise to the recent theoretical research that aims to build provably leakage-resilient cryptography. This direction is, however, very new and still largely lacks practitioners' evaluation with regard to both efficiency and practical security. A recent approach, One-Time Programs (OTPs), proposes using Yao's Garbled Circuit (GC) and very simple tamper-proof hardware to securely implement oblivious transfer, to guarantee leakage resilience. Our main contributions are (i) a generic architecture for using GC/ OTP modularly, and (ii) hardware implementation and efficiency analysis of GC/OTP evaluation. We implemented two FPGA-based prototypes: a system-on-a-programmable-chip with access to hardware crypto accelerator (suitable for smartcards and future smartphones), and a stand-alone hardware implementation (suitable for ASIC design). We chose AES as a representative complex function for implementation and measurements. As a result of this work, we are able to understand, evaluate and improve the practicality of employing GC/OTP as a leakage-resistance approach.