A note on the confinement problem
Communications of the ACM
Examining Smart-Card Security under the Threat of Power Analysis Attacks
IEEE Transactions on Computers
A Practical Implementation of the Timing Attack
CARDIS '98 Proceedings of the The International Conference on Smart Card Research and Applications
Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Secure Elliptic Curve Implementations: An Analysis of Resistance to Power-Attacks in a DSP Processor
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
The Intel 80x86 Processor Architecture: Pitfalls for Secure Systems
SP '95 Proceedings of the 1995 IEEE Symposium on Security and Privacy
Power-Analysis Attack on an ASIC AES implementation
ITCC '04 Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04) Volume 2 - Volume 2
Security as a new dimension in embedded system design
Proceedings of the 41st annual Design Automation Conference
Simulation models for side-channel information leaks
Proceedings of the 42nd annual Design Automation Conference
Power Attacks on Secure Hardware Based on Early Propagation of Data
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Remote timing attacks are practical
SSYM'03 Proceedings of the 12th conference on USENIX Security Symposium - Volume 12
Advances on access-driven cache attacks on AES
SAC'06 Proceedings of the 13th international conference on Selected areas in cryptography
Towards security limits in side-channel attacks
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Pinpointing the side-channel leakage of masked AES hardware implementations
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Automated design of cryptographic devices resistant to multiple side-channel attacks
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Cache attacks and countermeasures: the case of AES
CT-RSA'06 Proceedings of the 2006 The Cryptographers' Track at the RSA conference on Topics in Cryptology
Practical second-order DPA attacks for masked smart card implementations of block ciphers
CT-RSA'06 Proceedings of the 2006 The Cryptographers' Track at the RSA conference on Topics in Cryptology
Masked dual-rail pre-charge logic: DPA-resistance without routing constraints
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Security evaluation against electromagnetic analysis at design time
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
The “backend duplication” method
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Template attacks on masking—resistance is futile
CT-RSA'07 Proceedings of the 7th Cryptographers' track at the RSA conference on Topics in Cryptology
A digital design flow for secure integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Physical Design of FPGA Interconnect to Prevent Information Leakage
ARC '08 Proceedings of the 4th international workshop on Reconfigurable Computing: Architectures, Tools and Applications
Analysis and mitigation of process variation impacts on Power-Attack Tolerance
Proceedings of the 46th Annual Design Automation Conference
Garbled circuits for leakage-resilience: hardware implementation and evaluation of one-time programs
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
An exploration of L2 cache covert channels in virtualized environments
Proceedings of the 3rd ACM workshop on Cloud computing security workshop
Proceedings of the 4th International Workshop on Network on Chip Architectures
Role of power grid in side channel attack and power-grid-aware secure design
Proceedings of the 50th Annual Design Automation Conference
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While cryptographic algorithms are usually strong against mathematical attacks, their practical implementation, both in software and in hardware, opens the door to side-channel attacks. Without expensive equipment or intrusive monitoring, these attacks bypass the mathematical complexity and find the cryptographic key by observing the power consumption or the execution time variations of the device in normal operation mode. The power traces of 8000 encryptions are for instance sufficient to extract the secret key of an unprotected ASIC AES implementation, which is orders of magnitude smaller than the 2128 tests required to brute force the algorithm. A careful implementation can address these vulnerabilities, yet the solutions conflict with the common design goals to optimize for area, performance and power consumption. This paper introduces the side-channel attack pitfalls, which help create or facilitate the observation of the information leakage, discusses mitigation strategies and identifies opportunities for future research.