Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
ElectroMagnetic Analysis (EMA): Measures and Counter-Measures for Smart Cards
E-SMART '01 Proceedings of the International Conference on Research in Smart Cards: Smart Card Programming and Security
Low Cost Attacks on Tamper Resistant Devices
Proceedings of the 5th International Workshop on Security Protocols
Energy-efficient data scrambling on memory-processor interfaces
Proceedings of the 2003 international symposium on Low power electronics and design
Security wrappers and power analysis for SoC technologies
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
SECA: security-enhanced communication architecture
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
A methodology for mapping multiple use-cases onto networks on chips
Proceedings of the conference on Design, automation and test in Europe: Proceedings
NOC-centric Security of Reconfigurable SoC
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Design principles for tamper-resistant smartcard processors
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Proceedings of the 44th annual Design Automation Conference
Protecting bus-based hardware IP by secret sharing
Proceedings of the 45th annual Design Automation Conference
A security monitoring service for NoCs
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip
Proceedings of the 40th Annual International Symposium on Computer Architecture
| Hi-index | 0.00 |
After gaining popularity as a method of authentication in the form of smart cards, electronic security mechanisms are making their way into the domain of embedded domain with the goal of protecting Intellectual Property or for Digital Rights Management. A key role in implementing security at chip-level is played by the interconnect, which has the task of providing and regulating the flow of data between an increasing number of on-chip elements, not all of which can be considered trustworthy. Networks-on-Chip are emerging as a scalable solution for modern on-chip communication. In this study we aim to improve NoC security by forcing the messages to be routed on multiple disjoint paths, optionally in a non-deterministic manner. We implement our proposal and find it to have a reasonably low cost in terms of hardware area, although potentially having a larger overhead in terms of allocated bandwidth.