CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
Bit Permutation Instructions for Accelerating Software Cryptography
ASAP '00 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Speeding Up AES By Extending a 32 bit Processor Instruction Set
ASAP '06 Proceedings of the IEEE 17th International Conference on Application-specific Systems, Architectures and Processors
Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)
Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)
Fast and Efficient Implementation of AES via Instruction Set Extensions
AINAW '07 Proceedings of the 21st International Conference on Advanced Information Networking and Applications Workshops - Volume 01
Protecting AES Software Implementations on 32-Bit Processors Against Power Analysis
ACNS '07 Proceedings of the 5th international conference on Applied Cryptography and Network Security
Provably secure masking of AES
SAC'04 Proceedings of the 11th international conference on Selected Areas in Cryptography
Instruction set extensions for efficient AES implementation on 32-bit processors
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Prototype IC with WDDL and differential routing – DPA resistance assessment
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Improving first order differential power attacks through digital signal processing
Proceedings of the 3rd international conference on Security of information and networks
SCA-resistant embedded processors: the next generation
Proceedings of the 26th Annual Computer Security Applications Conference
On side-channel resistant block cipher usage
ISC'10 Proceedings of the 13th international conference on Information security
A first step towards automatic application of power analysis countermeasures
Proceedings of the 48th Design Automation Conference
Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library
Proceedings of the 48th Design Automation Conference
Implementation and evaluation of an SCA-resistant embedded processor
CARDIS'11 Proceedings of the 10th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Sleuth: automated verification of software power analysis countermeasures
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
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In recent years, different instruction set extensions for cryptography have been proposed for integration into general-purpose RISC processors. Both public-key and secret-key algorithms can profit tremendously from a small set of custom instructions specifically designed to accelerate performance-critical code sections. While the impact of instruction set extensions on performance and silicon area has been widely investigated in the recent past, the resulting security aspects (i.e. resistivity to side-channel attacks) of this particular design approach remain an open research topic. In this paper we discuss and analyze different techniques for increasing the side-channel resistance of AES software implementations using instruction set extensions. Furthermore, we propose a combination of hardware and software-related countermeasures and investigate the resulting effects on performance, cost, and security. Our experimental results show that a moderate degree of protection can be achieved with a simple software countermeasure. Hardware countermeasures, such as the implementation of security-critical functional units using a DPA-resistant logic style, lead to much higher resistance against side-channel attacks at the cost of a moderate increase in silicon area and power consumption.