Designing power analysis resistant and high performance block cipher coprocessor using WDDL and wave-pipelining

Authors:
Yuanman Tong;Zhiying Wang;Kui Dai;Hongyi Lu
Affiliations:
School of Computer Science, National University of Defense Technology, Changsha, Hunan, P.R.C.;School of Computer Science, National University of Defense Technology, Changsha, Hunan, P.R.C.;School of Computer Science, National University of Defense Technology, Changsha, Hunan, P.R.C.;School of Computer Science, National University of Defense Technology, Changsha, Hunan, P.R.C.
Venue:
Inscrypt'06 Proceedings of the Second SKLOIS conference on Information Security and Cryptology
Year:
2006

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Abstract

Novel design method and design flow of block cipher coprocessor is presented based on the WDDL (Wave Dynamic Differential Logic) and Wave-Pipelining techniques. This design flow utilized the current commercially available EDA (Electronic Design Automatic) tools to a large degree. The WDDL and wave-pipelining based coprocessor not only resists power analysis, but also achieves high performance and low power consumption in nature. According to the design flow, this paper implements a DES coprocessor. The simulation results show that the novel design method does achieve high performance, low power consumption and power analysis resistant ability at the cost of chip area.