Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Asynchronous System on Chip Interconnect
Asynchronous System on Chip Interconnect
Simple Circuits that Work for Complicated Reasons
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Proceedings of the conference on Design, automation and test in Europe
Jitter Measurements of High-Speed Serial Links
IEEE Design & Test
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
Registers for phase difference based logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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A novel self-timed communication protocol is based upon phase-modulation of a reference signal. The reference and the data are sent on the same transmission lines and the data can be recovered observing the sequence of events on the same lines. The sender block consists of a reference generator and variable-delay elements, while the receiver includes a delay-locked loop for synchronization and a mutual exclusion element with additional logic (validity bit and FIFO) for data recovery. This protocol exhibits high robustness with respect to transient errors caused by narrow pulse interference, usually associated with crosstalk and radiation.