Performance-driven clustering of asynchronous circuits

Authors:
Georgios D. Dimou;Peter A. Beerel;Andrew M. Lines
Affiliations:
Fulcrum Microsystems Inc., Calabasas, CA;Fulcrum Microsystems Inc., Calabasas, CA and Ming Hsieh Dept. of Elec. Eng., University of Southern California, Los Angeles, CA;Fulcrum Microsystems Inc., Calabasas, CA
Venue:
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Year:
2011

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Abstract

This paper describes a novel approach for generating asynchronous circuits from HDL specifications by clustering the synthesized gates into asynchronous pipeline stages while preserving liveness, meeting throughput constraints, and minimizing area. The method enables a form of automatic repipelining in which the throughput of the resulting design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The method is design-style agnostic and is thus applicable to many asynchronous design styles.