Design of low-power high-speed truncation-error-tolerant adder and its application in digital signal processing

Authors:
Ning Zhu;Wang Ling Goh;Weija Zhang;Kiat Seng Yeo;Zhi Hui Kong
Affiliations:
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore;School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore;School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore;School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore;School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

Citing 9
Cited 8

Defect and Error Tolerance in the Presence of Massive Numbers of Defects

IEEE Design & Test
Intelligible Test Techniques to Support Error-Tolerance

ATS '04 Proceedings of the 13th Asian Test Symposium
Let's Think Analog

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Energy Aware Computing through Probabilistic Switching: A Study of Limits

IEEE Transactions on Computers
Analysis and Testing for Error Tolerant Motion Estimation

DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms

DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Error-Tolerance and Multi-Media

IIH-MSP '06 Proceedings of the 2006 International Conference on Intelligent Information Hiding and Multimedia
Reduction of detected acceptable faults for yield improvement via error-tolerance

Proceedings of the conference on Design, automation and test in Europe
Low Voltage, Low Power VLSI Subsystems

Low Voltage, Low Power VLSI Subsystems

MACACO: modeling and analysis of circuits for approximate computing

Proceedings of the International Conference on Computer-Aided Design
Accuracy-configurable adder for approximate arithmetic designs

Proceedings of the 49th Annual Design Automation Conference
Modeling and synthesis of quality-energy optimal approximate adders

Proceedings of the International Conference on Computer-Aided Design
Substitute-and-simplify: a unified design paradigm for approximate and quality configurable circuits

Proceedings of the Conference on Design, Automation and Test in Europe
Improving energy gains of inexact DSP hardware through reciprocative error compensation

Proceedings of the 50th Annual Design Automation Conference
On reconfiguration-oriented approximate adder design and its application

Proceedings of the International Conference on Computer-Aided Design
An energy efficient approximate adder with carry skip for error resilient neuromorphic VLSI systems

Proceedings of the International Conference on Computer-Aided Design
Approximate logic synthesis under general error magnitude and frequency constraints

Proceedings of the International Conference on Computer-Aided Design

Quantified Score

Hi-index	0.00

Visualization

Abstract

In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 65% improvement in the Power-Delay Product (PDP). One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors.