ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Estimating Error Rate in Defective Logic Using Signature Analysis
IEEE Transactions on Computers
Reduction of detected acceptable faults for yield improvement via error-tolerance
Proceedings of the conference on Design, automation and test in Europe
Multi-vector tests: a path to perfect error-rate testing
Proceedings of the conference on Design, automation and test in Europe
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Yield analysis of partial defect tolerant bit-plane array
Computers & Mathematics with Applications
Software adaptation in quality sensitive applications to deal with hardware variability
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Approximate logic synthesis for error tolerant applications
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Error Rate Estimation for Defective Circuits via Ones Counting
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Accuracy-configurable adder for approximate arithmetic designs
Proceedings of the 49th Annual Design Automation Conference
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Journal of Electronic Testing: Theory and Applications
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
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We have developed a new digital system mode of operation, refereed to as error-tolerance, the purpose of which is to increase effective yield. Errortolerance is based on the fact that many digital systems exhibit acceptable behavior even though they contain defects and occasionally output errors. A radically new test methodology, called intelligible testing, is required to support error-tolerance. This paper addresses parts of this methodology. There are several fundamental philosophical differences between intelligible testing and classical testing, such as: intelligible testing is application oriented; it partitions die and chips into multiple categories, not just good and bad parts; and it supplies quantitative information about the effects of defects on errors, i.e. it is error based rather than fault based. We describe three types of error attributes, namely error-rate, error-accumulation (retention), and errorsignificance. We present test techniques for estimating quantitative values for these qualitative attributes. Testing to support error-tolerance involves new ATPG tools, new fault simulators, and new DFT and BIST techniques.