VCLEARIT: a VLSI CMOS circuit leakage reduction technique for nanoscale technologies
ACM SIGARCH Computer Architecture News - Special issue: ALPS '07---advanced low power systems
A low-power transmission-gate-based 16-bit multiplier for digital hearing aids
Analog Integrated Circuits and Signal Processing
Experimental analysis of sequence dependence on energy saving for error tolerant image processing
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Performance comparison of multipliers for power-speed trade-off in VLSI design
ICNVS'10 Proceedings of the 12th international conference on Networking, VLSI and signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A hierarchical design of high performance 8x8 bit multiplier based on Vedic mathematics
Proceedings of the 2011 International Conference on Communication, Computing & Security
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells
Microelectronics Journal
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Designers developing the low voltage, low power chips that enable small, portable devices, face a very particular set of challenges. This monograph details cutting-edge design techniques for the low power circuitry required by the many new miniaturized business and consumer products driving the electronics market. Table of contentsChapter 1: Low-Power CMOS VLSI DesignChapter 2: Circuit Techniques for Low-Power DesignChapter 3: Low-Voltage Low-Power Adders Chapter 4: Low-Voltage Low-Power MultipliersChapter 5: Low-Voltage Low-Power Read-Only Memories Chapter 6: Low-Voltage Low-Power Static Random-Access MemoriesChapter 7: Low-Voltage Low-Power Dynamic Random-Access Chapter 8: Large Low-Power VLSI System Design and ApplicationsIndex