Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Power Aware Design Methodologies
Power Aware Design Methodologies
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LECTOR: a technique for leakage reduction in CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A combined gate replacement and input vector control approach for leakage current reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Voltage, Low Power VLSI Subsystems
Low Voltage, Low Power VLSI Subsystems
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel methodology to reduce leakage power in CMOS complementary circuits
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Leakage power loss is a major concern in deep-submicron technologies as it drains the battery even when a circuit is completely idle. In this paper, we first present a novel leakage reduction technique and then compare and contrast it with other well established leakage reduction techniques. Our leakage reduction technique achieves cancellation of leakage effects in both the pull-up network (PUN) as well as the pull-down network (PDN) for CMOS circuits. It involves voltage balancing in the PUN and PDN paths using a combination of high-VT (high voltage threshold) and standard-VT sleep transistors. Experiments conducted on a variety of multi-level combinational MCNC'91 benchmarks show significant savings in leakage power (upto 3 orders of magnitude), with lesser area and delay penalty using our leakage reduction technique when compared to other techniques.