Practical low power digital VLSI design
Practical low power digital VLSI design
Low-Power CMOS Design
Low Power Digital CMOS Design
A novel 32-bit scalable multiplier architecture
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Minimization of switching activities of partial products for designing low-power multipliers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
ASIC Implementation of 4 Bit Multipliers
ICETET '08 Proceedings of the 2008 First International Conference on Emerging Trends in Engineering and Technology
Low Voltage, Low Power VLSI Subsystems
Low Voltage, Low Power VLSI Subsystems
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In this paper, low power and high speed 8x8 Bit Vedic Multiplier is presented. A Novel technique for digit multiplication is produced that is quite different from the conventional method of multiplication like Add and Shift [1]. This paper presents a systematic design methodology for fast and delay efficient Vedic Multiplier based on Vedic Mathematics [2]. The multiplier architecture based on the Vertical and Crosswise algorithm of Ancient Indian Vedic Mathematics. In this paper, general technique for NxN multiplication is proposed and implemented; this gives less delay for calculating the multiplication results for 8x8 Bit Vedic Multiplier. In this paper, less delay and high speed 8x8 Bit Vedic Multiplier is presented. The multiplier cell of the adder is designed by using Pass Transistor (n-transistor), p-transistor used as cross coupled devices. The 8x8 Bit Vedic Multiplier circuit has been simulated using Microwind 3.1 VLSI Layout CAD tools. Simulated results for proposed 8x8 bit Vedic Multiplier circuit shows a great reduction in delay for 0.18 μm.