Logic architecture and VDD selection for reducing the impact of intra-die random VT variations on timing

Authors:
Bahman Kheradmand-Boroujeni;Christian Piguet;Yusuf Leblebici
Affiliations:
Integrated and Wireless Systems, Centre Suisse d'Electronique et de Microtechnique, Neuchâtel, Switzerland and Microelectronic Systems Laboratory, Ecole Polytechnique Fédérale de La ...;Integrated and Wireless Systems, Centre Suisse d'Electronique et de Microtechnique, Neuchâtel, Switzerland;Microelectronic Systems Laboratory, Ecole Polytechnique Fédérale de Lausanne, Lausanne, Switzerland
Venue:
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Year:
2010

Citing 2
Cited 0

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Proceedings of the Conference on Design, Automation and Test in Europe

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Abstract

We show that in logic circuits working at supply voltage (VDD) below nominal value, proper selection of logic architecture and VDD together can reduce the impact of device-to-device random process variations (PV) on timing. First we show that σ/µ of transistor current and delay strongly depend on VDD. Then we compare the PV sensitivity of Low-Power Slow (LP-S) and High-Power Fast (HP-F) architectures. The results propose the idea that for a given technology, equal power budget and delay, LP-S circuits working at higher VDD are about 1.8X less PV sensitive compare to HP-F circuits working at lower VDD.