An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes

Authors:
Zhigang Jiang;Sandeep K. Gupta
Affiliations:
-;-
Venue:
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Year:
2002

Citing 0
Cited 7

Defect and Error Tolerance in the Presence of Massive Numbers of Defects

IEEE Design & Test
A framework for system reliability analysis considering both system error tolerance and component test quality

Proceedings of the conference on Design, automation and test in Europe
Reduction of detected acceptable faults for yield improvement via error-tolerance

Proceedings of the conference on Design, automation and test in Europe
Threshold testing: improving yield for nanoscale VLSI

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dynamic effort scaling: managing the quality-efficiency tradeoff

Proceedings of the 48th Design Automation Conference
Managing the Quality vs. Efficiency Trade-off Using Dynamic Effort Scaling

ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Probabilistic Embedded Computing
A Simulated Annealing Inspired Test Optimization Method for Enhanced Detection of Highly Critical Faults and Defects

Journal of Electronic Testing: Theory and Applications

Quantified Score

Hi-index	0.00

Visualization

Abstract

When VLSI scaling reaches closer to the limits of laws of physics and to the limits of fabrication processes, yields will decrease, especially at desired speed. However, for a large class of applications, chips need not be perfect to be acceptable. In this paper, we describe the notion of threshold testing that can help improve effective yield for future processes. We then develop an ATPG and demonstrate that significant increase in effective yield can be attained at negligible increase in test application cost.