An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation

Authors:
Yifeng Qiu;Wael Badawy;Robert Turney
Affiliations:
Department of Electrical and Computer Engineering, University of Calgary, Alberta, Canada;Department of Electrical and Computer Engineering, University of Calgary, Alberta, Canada;DSP Division, MVI Group, Xilinx Inc., Watertown, USA 53094
Venue:
Journal of Signal Processing Systems
Year:
2009

Citing 4
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Abstract

A new integrated programmable platform architecture is presented, with the support of multiple accelerators and extensible processing cores. An advanced application for this architecture is to facilitate the implementation of H.264 baseline profile video codec. The platform architecture employs the novel concept of virtual socket and optimized memory access to increase the efficiency for video encoding. The proposed architecture is mapped on an integrated FPGA device, Annapolis WildCard-II驴 or WildCard-4驴, for verification. According to the evaluation under different configurations, the results show that the overall performance of the architecture, with the integrated accelerators, can sufficiently meet the real-time encoding requirement for H.264 BP at basic levels, and achieve about 2---5.5 and 1---3 dB improvement, in terms of PSNR, as compared with MPEG-2 MP and MPEG-4 SP, respectively. The architecture is highly extensible, and thus can be utilized to benefit the development of multi-standard video codec beyond the description in this paper.