Estimation of speed, area, and power of parameterizable, soft IP

Authors:
Jagesh Sanghavi;Albert Wang
Affiliations:
Tensilica, Inc.;Tensilica, Inc.
Venue:
Proceedings of the 38th annual Design Automation Conference
Year:
2001

Citing 1
Cited 1

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A quantitative study and estimation models for extensible instructions in embedded processors

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Abstract

We present a new approach to estimate speed, area, and power of a parameterizable, soft IP. By running the ASIC implementation flow only on selected configurations, we predict the performance for any arbitrary configuration. We exploit performance function decomposability to address the combinatorial explosion challenge. The estimator has been used successfully to configure Xtensa processor cores for numerous embedded SOC designs.