CReconfigurable finite field instruction set architecture

Authors:
Nathan Jachimie;Fernando Martinez-Vallin;Jafar Saniie
Affiliations:
Illinois Institute of Technology, Chicago, Illinois;Illinois Institute of Technology, Chicago, Illinois;Illinois Institute of Technology, Chicago, Illinois
Venue:
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Year:
2007

Citing 7
Cited 0

Introduction to finite fields and their applications

Introduction to finite fields and their applications
Xtensa: A Configurable and Extensible Processor

IEEE Micro
Error Control Coding, Second Edition

Error Control Coding, Second Edition
Evaluating Instruction Set Extensions for Fast Arithmetic on Binary Finite Fields

ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields

SBAC-PAD '04 Proceedings of the 16th Symposium on Computer Architecture and High Performance Computing
Instruction Set Extensions for Reed-Solomon Encoding and Decoding

ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography

Proceedings of the conference on Design, automation and test in Europe: Proceedings

Quantified Score

Hi-index	0.00

Visualization

Abstract

Reconfigurable computing can provide a significant speed-up factor to cryptographic and error correcting code algorithms. Finite field arithmetic is essential to both, but is difficult to implement efficiently. Finite field instruction set extensions and a reconfiguration framework have been constructed to enable a finite field multiplier to be regenerated via software control. A performance evaluation has been created by generating a Finite Field Extensions Unit with MicroBlaze processor in a Xilinx Virtex2Pro FPGA. By utilizing the in-system partial reconfiguration capability, the finite field multiplier can be customized to a particular size and definition. With a customized GF(2163 ) multiplier, a speed-up factor of 1530X has been demonstrated versus execution of the same algorithm on the MicroBlaze processor alone.