A self-optimizing embedded microprocessor using a loop table for low power

The filter cache: an energy efficient memory structure

MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture

Putting the fill unit to work: dynamic optimizations for trace cache microprocessors

MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture

An ASIP design methodology for embedded systems

CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign

Customized instruction-sets for embedded processors

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Instruction fetch energy reduction using loop caches for embedded applications with small tight loops

ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design

A power reduction technique with object code merging for application specific embedded processors

DATE '00 Proceedings of the conference on Design, automation and test in Europe

A low power unified cache architecture providing power and performance flexibility (poster session)

ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design

A first-step towards an architecture tuning methodology for low power

CASES '00 Proceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems

Platform Tuning for Embedded Systems Design

Computer

Xtensa: A Configurable and Extensible Processor

IEEE Micro

Energy and Performance Improvements in Microprocessor Design Using a Loop Cache

ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design