Evaluation of ASIPs Design with LISATek

Authors:
Rashid Muhammad;Ludovic Apvrille;Renaud Pacalet
Affiliations:
System-on-Chip laboratory, LabSoC, GET/ENST, Sophia-Antipolis, France;System-on-Chip laboratory, LabSoC, GET/ENST, Sophia-Antipolis, France;System-on-Chip laboratory, LabSoC, GET/ENST, Sophia-Antipolis, France
Venue:
SAMOS '08 Proceedings of the 8th international workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Year:
2008

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Abstract

This paper evaluates an ASIP design methodology based on the extension of an existing instruction set and architecture described with LISA 2.0 language. The objective is to accelerate the ASIPs design process by using partially predefined, configurable RISC-like embedded processor cores that can be quickly tuned to given applications by means of ISE (Instruction Set Extension) techniques. A case study demonstrates the methodological approach for the JPEG algorithm.