Xtensa with User Defined DSP Coprocessor Microarchitectures

Authors:
Gulbin Ezer
Affiliations:
-
Venue:
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Year:
2000

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Abstract

This paper describes the third generation configurable and extensible Xtensa (tm) processor with enhanced DSP functionality targeted to System-On-Chip (SOC) designs. Xtensa III processor family can be configured with an IEEE-compatible floating point unit (FPU) and/or a powerful, energy efficient Vector Integer coprocessor, both implemented using Tensilica Instruction Extension (TIE) language and automatically integrated with the Xtensa base processor core.