Simultaneous multithreading: maximizing on-chip parallelism
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Hardware/software codesign of finite field datapath for low-energy Reed-Solomon codecs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Future wireless convergence platforms
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Instruction set extensions for software defined radio on a multithreaded processor
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Instruction Set Extensions for Reed-Solomon Encoding and Decoding
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
IEEE Micro
Software defined radio – a high performance embedded challenge
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
Observations on power-efficiency trends in mobile communication devices
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
IEEE Transactions on Computers
Reconfigurable terminals: an overview of architectural solutions
IEEE Communications Magazine
A software-defined communications baseband design
IEEE Communications Magazine
Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
New architectures for fast convolutional encoders and threshold decoders
IEEE Journal on Selected Areas in Communications
Domain specific architecture for next generation wireless communication
Proceedings of the Conference on Design, Automation and Test in Europe
| Hi-index | 0.00 |
Software defined radios provide programmable solutions for implementing the physical layer processing of multiple communication standards. Mobile devices implementing these standards require high-performance processors to perform high-bandwidth physical layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including cyclic redundancy checking, convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. We also present hardware designs for implementing these extensions, along with estimates of their area, critical path delay, and power consumption. The performance benefits of these extensions are evaluated using a supercomputer-class vectorizing compiler and the Sandblaster low-power multithreaded processor for software defined radio. The proposed instruction set extensions provide significant performance improvements at relatively low cost, while maintaining a high degree of programmability.