Hardware for multiconnected networks: the design flow
Information Sciences—Informatics and Computer Science: An International Journal - Special issue: Informatics and computer science intelligent systems applications
Instruction set extensions for software defined radio
Microprocessors & Microsystems
Design and implementation of a field programmable CRC circuit architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High speed VLSI architecture for general linear feedback shift register (LFSR) structures
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
High performance multi-node file copies and checksums for clustered file systems
LISA'10 Proceedings of the 24th international conference on Large installation system administration
High speed CRC with 64-bit generator polynomial on an FPGA
ACM SIGARCH Computer Architecture News
Resilient microring resonator based photonic networks
Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture
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This paper presents a theoretical result in the context of realizing high-speed hardware for parallel CRC checksums. Starting from the serial implementation widely reported in the literature, we have identified a recursive formula from which our parallel implementation is derived. In comparison with previous works, the new scheme is faster and more compact and is independent of the technology used in its realization. In our solution, the number of bits processed in parallel can be different from the degree of the polynomial generator. Last, we have also developed high-level parametric codes that are capable of generating the circuits autonomously when only the polynomial is given.