A multi-level view of dependable computing
Computers and Electrical Engineering
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Exploitation of optical interconnects in future server architectures
IBM Journal of Research and Development - POWER5 and packaging
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Firefly: illuminating future network-on-chip with nanophotonics
Proceedings of the 36th annual international symposium on Computer architecture
Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
Analysis of photonic networks for a chip multiprocessor using scientific applications
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
On hamming product codes with type-II hybrid ARQ for on-chip interconnects
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
Proceedings of the 37th annual international symposium on Computer architecture
Performance Evaluation of a Multicore System with Optically Connected Memory Modules
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Performability/energy tradeoff in error-control schemes for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Addressing system-level trimming issues in on-chip nanophotonic networks
HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
IEEE Transactions on Computers
Proceedings of the 26th ACM international conference on Supercomputing
Tolerating process variations in nanophotonic on-chip networks
Proceedings of the 39th Annual International Symposium on Computer Architecture
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Microring resonator-based photonic interconnects are being considered for both on-chip and off-chip communication in order to satisfy the power and bandwidth requirements of future large scale chip multiprocessors. However, microring resonators are prone to malfunction due to fabrication errors, and they are also extremely sensitive to fluctuations in temperature. In this paper we derive a fault model for microring based optical links that can be used by computer architects to make informed design choices. We evaluate different schemes for improving resilience, such as retransmission versus error-correction, using an optical fault simulator based on our fault model. We show how meeting a target mean time between failures (MTBF) affects the choice of resilience scheme - our investigation indicates that until fault rates are in the range of 10−21 to 10−24 per cycle, error detection/correction schemes will be needed in order to meet a 1M hour MTBF. We also evaluate how the resilience scheme impacts the performance of the link, which will help an architect choose the appropriate scheme based on the throughput requirements of a particular design.