Computation of cyclic redundancy checks via table look-up
Communications of the ACM
Fast software implementation of error detection codes
IEEE/ACM Transactions on Networking (TON)
Automatic Generation of Parallel CRC Circuits
IEEE Design & Test
32-Bit Cyclic Redundancy Codes for Internet Applications
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Parallel CRC Computation in FPGAs
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Cyclic Redundancy Code (CRC) Polynomial Selection For Embedded Networks
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
Implementation of fast CRC calculation
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A scalable and high performance software iSCSI implementation
FAST'05 Proceedings of the 4th conference on USENIX Conference on File and Storage Technologies - Volume 4
IEEE Transactions on Computers
High speed CRC with 64-bit generator polynomial on an FPGA
ACM SIGARCH Computer Architecture News
Application space exploration of a heterogeneous run-time configurable digital signal processor
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The design and implementation of a programmable cyclic redundancy check (CRC) computation circuit architecture, suitable for deployment in network related system-on-chips (SoCs) is presented. The architecture has been designed to be field reprogrammable so that it is fully flexible in terms of the polynomial deployed and the input port width. The circuit includes an embedded configuration controller that has a low reconfiguration time and hardware cost. The circuit has been synthesised and mapped to 130-nm UMC standard cell [application-specific integrated circuit (ASIC)] technology and is capable of supporting line speeds of 5 Gb/s.