Design and implementation of HDLC procedures based on FPGA
ASID'09 Proceedings of the 3rd international conference on Anti-Counterfeiting, security, and identification in communication
Design and implementation of a field programmable CRC circuit architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High speed CRC with 64-bit generator polynomial on an FPGA
ACM SIGARCH Computer Architecture News
| Hi-index | 0.00 |
CRC is important for error detection in communication systems. With transmission speeds of several Gb/s the high-speed implementation is a bottleneck. A circuit with two parallel calculation units has been implemented in a 0.35 micron process. They use 32 bits and 64 bits parallel input respectively. Chip measurements prove throughput higher than 5.76 Gb/s, which indicates that 10 Gb/s throughput is possible in more modern processes.