Instruction set extensions for software defined radio on a multithreaded processor
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
Instruction set extensions for software defined radio
Microprocessors & Microsystems
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Several new architectures for high-speed convolution encoders and threshold decoders are developed. In particular, it is shown that new architectures featuring both parallelism and pipelining are promising from a speed point of view. These architectures are practical for a wide range of coding rates and constant lengths. Two integrated circuits featuring these architectures have been designed and fabricated in a CMOS 3-μm technology. The two circuits have been tested and can be used to build convolutional encoders and definite threshold decoders operating at data rates above 100 Mb/s. It is shown that with these architectures, encoders and threshold decoders could easily be designed to operate at data rates above 1 Gb/s