Instruction-level parallel processing: history, overview, and perspective
The Journal of Supercomputing - Special issue on instruction-level parallelism
Cycle and phase accurate DSP modeling and integration for HW/SW co-verification
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An efficient architecture model for systematic design of application-specific multiprocessor SoC
Proceedings of the conference on Design, automation and test in Europe
Architectural simulation in the context of behavioral synthesis
Proceedings of the conference on Design, automation and test in Europe
DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes a design approach based on integrated architectural and system-on-chip (SoC) simulations. The main idea is to have an efficient framework for the design and the evaluation of multimedia terminals, allowing a fast system simulation with a definable degree of accuracy. The design approach includes the simulation of very long instruction word (VLIW) digital signal processors (DSPs), the utilization of a device multiplexing the media streams, and the emulation of the real-time media acquisition. This methodology allows the evaluation of both the multimedia algorithm implementations and the hardware platform, giving feedback on the complete SoC including the interaction between modules and conflicts in accessing either the bus or shared resources. An instruction set architecture (ISA) simulator and an SoC simulation environment compose the integrated framework. In order to validate this approach, the evaluation of an audio-video multiprocessor terminal is presented, and the complete simulation test results are reported.