Architectural support for fast symmetric-key cryptography
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Design of Low-power Baseband-processor for RFID Tag
SAINT-W '06 Proceedings of the International Symposium on Applications on Internet Workshops
Fast and Efficient Implementation of AES via Instruction Set Extensions
AINAW '07 Proceedings of the 21st International Conference on Advanced Information Networking and Applications Workshops - Volume 01
A Survey of Lightweight-Cryptography Implementations
IEEE Design & Test
PRESENT: An Ultra-Lightweight Block Cipher
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Light-Weight Instruction Set Extensions for Bit-Sliced Cryptography
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Ultra-Lightweight Implementations for Smart Devices --- Security for 1000 Gate Equivalents
CARDIS '08 Proceedings of the 8th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Instruction Set Extensions for Enhancing the Performance of Symmetric-Key Cryptography
ACSAC '08 Proceedings of the 2008 Annual Computer Security Applications Conference
Related-key rectangle attack on 36 rounds of the XTEA block cipher
International Journal of Information Security
Boosting AES performance on a tiny processor core
CT-RSA'08 Proceedings of the 2008 The Cryptopgraphers' Track at the RSA conference on Topics in cryptology
SAC'10 Proceedings of the 17th international conference on Selected areas in cryptography
Hardware Implementation of a Flexible Tag Platform for Passive RFID Devices
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
SEA: a scalable encryption algorithm for small embedded applications
CARDIS'06 Proceedings of the 7th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
Instruction set extensions for efficient AES implementation on 32-bit processors
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Linear cryptanalysis of reduced-round PRESENT
CT-RSA'10 Proceedings of the 2010 international conference on Topics in Cryptology
EPCBC: a block cipher suitable for electronic product code encryption
CANS'11 Proceedings of the 10th international conference on Cryptology and Network Security
Compact implementation and performance evaluation of block ciphers in ATtiny devices
AFRICACRYPT'12 Proceedings of the 5th international conference on Cryptology in Africa
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Due to the continuously increasing design complexity of passive radio-frequency identification (RFID) tags, relying on microcontroller-based architectures will become vital in the future. Re-using the microcontroller for multiple tasks, e.g., protocol handling and computing cryptographic algorithms is advantageous from a system point-of-view. In this work we present instruction-set extensions (ISEs) for minimizing the hardware-implementation costs of symmetric-key algorithms on a synthesizable 8-bit microcontroller. We have analyzed the block ciphers: Present-80, SEA96,8, and XTEA. Integrating ISEs has reduced the hardware-implementation costs by 4 to 48%. When considering the re-use of the microcontroller for protocol handling, overhead costs for implementing encryption and decryption functionality of the block ciphers are between 519 and 1 021 GEs for a 130 nm CMOS technology. Implementation costs for encryption-only versions are between 333 and 520 GEs. Our results emphasize that integrating ISEs for lowering the hardware-implementation costs of symmetric-key algorithms on low-resource microcontrollers is beneficial.