Two systolic architectures for modular multiplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Systolic Modular Multiplication
IEEE Transactions on Computers
A Hardware Algorithm for Modular Multiplication/Division
IEEE Transactions on Computers
Son of seminumerical algorithms
ACM SIGSAM Bulletin
| Hi-index | 14.98 |
A new systolic architecture for modular division is proposed in this paper. The architecture is based on a new hardware algorithm for modular division that is extended from the plus-minus algorithm for the greatest common divisor computation. Both the area complexity and the time complexity of the new architecture are linear with respect to the operand bit length. Compared to the architecture using a redundant number representation proposed by Kaihara and Takagi, the new architecture allows a doubled throughput due primarily to the greatly reduced critical path delay, while the area is only about 20 percent larger. Moreover, it is shown that, with a small addition to the control logic, the architecture can also be used to perform Montgomery modular multiplication, thereby efficiently realizing a unified modular multiplier/divider.