IEEE Transactions on Computers
Modulo Reduction in Residue Number Systems
IEEE Transactions on Parallel and Distributed Systems
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
The art of computer programming, volume 2 (3rd ed.): seminumerical algorithms
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Systolic Modular Multiplication
IEEE Transactions on Computers
An RNS Montgomery Modular Multiplication Algorithm
IEEE Transactions on Computers
Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Simplifying Quotient Determination in High-Radix Modular Multiplication
ARITH '95 Proceedings of the 12th Symposium on Computer Arithmetic
A VLSI Algorithm for Modular Multiplication/Division
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
Cox-Rower architecture for fast parallel montgomery multiplication
EUROCRYPT'00 Proceedings of the 19th international conference on Theory and application of cryptographic techniques
A New Systolic Architecture for Modular Division
IEEE Transactions on Computers
On the implementation of the discrete Fourier transform in the encrypted domain
IEEE Transactions on Information Forensics and Security
A high performance ROM-based structure for modular exponentiation
Computers and Electrical Engineering
Design of a new kind of encryption kernel based on RSA algorithm
CIS'05 Proceedings of the 2005 international conference on Computational Intelligence and Security - Volume Part II
International Journal of Applied Cryptography
International Journal of Applied Cryptography
Improving modular inversion in RNS using the plus-minus method
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
Hi-index | 14.98 |
A mixed radix-4/2 algorithm for modular multiplication/division suitable for VLSI implementation is proposed. The algorithm is based on Montgomery method for modular multiplication and on the extended Binary GCD algorithm for modular division. Both algorithms are modified and combined into the proposed algorithm so that almost all the hardware components are shared. The new algorithm carries out both calculations using simple operations such as shifts, additions, and subtractions. The radix-2 signed-digit representation is used to avoid carry propagation in all additions and subtractions. A modular multiplier/divider based on the algorithm performs an n{\hbox{-}}{\rm bit} modular multiplication/division in O(n) clock cycles where the length of the clock cycle is constant and independent of n. The modular multiplier/divider has a linear array structure with a bit-slice feature and can be implemented with much smaller hardware than that necessary to implement both multiplier and divider separately.