Implementing elliptic curve cryptography
Implementing elliptic curve cryptography
Low-Energy Digit-Serial/Parallel Finite Field Multipliers
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
VLSI Algorithms, Architectures, and Implementation of a Versatile GF(2m) Processor
IEEE Transactions on Computers
On Computing Multiplicative Inverses in GF(2/sup m/)
IEEE Transactions on Computers
Low Complexity Bit-Parallel Finite Field Arithmetic Using Polynomial Basis
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Fast Multiplication on Elliptic Curves over GF(2m) without Precomputation
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2n)
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
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Scalar multiplication is the most time consuming computation in elliptic curve cryptography (ECC). ECC coprocessors provide computational support for the scalar multiplication algorithm. In this paper, we propose an efficient multi-segment GF(2m) multiplication method and discuss its application for ECC. The proposed method is particularly effective when the underlying technology provides an efficient realization of dual-port RAM block structures. We implemented ECC coprocessors in FPGA development environments to compare the resource usages of the ECC processors which use the proposed multi-segment multipliers and others using the digit-serial multipliers. The experimental results show that the proposed multi-segment multiplication method requires significantly less FPGA resources for the same multiplication performance in ECC implementations.