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Lecture notes in computer sciences; 218 on Advances in cryptology---CRYPTO 85
Algebraic aspects of cryptography
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CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
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Finding Optimum Parallel Coprocessor Design for Genus 2 Hyperelliptic Curve Cryptosystems
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IEEE Transactions on Computers
HW/SW co-design of a hyperelliptic curve cryptosystem using a microcode instruction set coprocessor
Integration, the VLSI Journal - Special issue: Embedded cryptographic hardware
Efficient doubling on genus 3 curves over binary fields
CT-RSA'06 Proceedings of the 2006 The Cryptographers' Track at the RSA conference on Topics in Cryptology
Hardware/software co-design for hyperelliptic curve cryptography (HECC) on the 8051 µP
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
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Cryptographic algorithms are used in a large variety of different applications to ensure security services. It is, thus, very interesting to investigate various implementation platforms. Hyperelliptic curve schemes are cryptographic primitives to which a lot of attention was recently given due to the short operand size compared to other algorithms. They are specifically interesting for special-purpose hardware. This paper provides a comprehensive investigation of high-efficient HEC architectures. We propose a genus-2 hyperelliptic curve cryptographic coprocessor using affine coordinates. We implemented a special class of hyperelliptic curves, namely using the parameter h(x)=x and f=x5+f1x+f0 and the base field GF(289). In addition, we only consider the most frequent case in our implementation and assume that the other cases are handled, e.g. by the protocol. We provide three different implementations ranging from high speed to moderate area. Hence, we provide a solution for a variety of applications. Our high performance HECC coprocessor is 78.5% faster than the best previous implementation and our low area implementation utilizes only 22.7% of the area that the smallest published design uses. Taking into account both area and latency, our coprocessor is an order of magnitude more efficient than previous implementations. We hope that the work at hand provides a step towards introducing HEC systems in practical applications.