Efficient simultaneous inversion in parallel and application to point multiplication in ECC
CISC'05 Proceedings of the First SKLOIS conference on Information Security and Cryptology
Hyperelliptic curve coprocessors on a FPGA
WISA'04 Proceedings of the 5th international conference on Information Security Applications
Hardware/software co-design for hyperelliptic curve cryptography (HECC) on the 8051 µP
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Performance of HECC coprocessors using inversion-free formulae
ICCSA'06 Proceedings of the 2006 international conference on Computational Science and Its Applications - Volume Part III
A general methodology for pipelining the point multiplication operation in curve based cryptography
ACNS'06 Proceedings of the 4th international conference on Applied Cryptography and Network Security
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Hardware accelerators are often used in cryptographic applicationsfor speeding up the highly arithmetic-intensivepublic-key primitives, e.g. in high-end smart cards. Oneof these emerging and very promising public-key schemeis based on HyperElliptic Curve Cryptosystems (HECC).In the open literature only a few considerations deal withhardware implementation issues of HECC.Our contribution appears to be the first one to proposearchitectures for the latest findings in efficient grouparithmetic on HEC. The group operation of HECC allowsparallelization at different levels: bit-level parallelization(via different digit-sizes in multipliers) and arithmeticoperation-level parallelization (via replicated multipliers).We investigate the trade-offs between both parallelizationoptions and identify speed and time-area optimized configurations.We found that a coprocessor using a single multiplier(D = 8) instead of two or more is best suited. Thiscoprocessor is able to compute group addition and doublingin 479 and 334 clock cycles, respectively. Providing moreresources it is possible to achieve 288 and 248 clock cycles,respectively.