A new digit-serial systolic mulitplier for high performance GF(2m) applications

Authors:
Chang Hoon Kim;Soonhak Kwon;Chun Pyo Hong;In Gil Nam
Affiliations:
Dept. of Computer and Information Engineering, Daegu University, Jinryang, Kyungsan, Korea;Dept. of Mathematics and Institute of Basic Science, Sungkyunkwan University, Suwon, Korea;Dept. of Computer and Communication Engineering, Daegu University, Jinryang, Kyungsan, Korea;Dept. of Computer and Information Engineering, Daegu University, Jinryang, Kyungsan, Korea
Venue:
HPCC'05 Proceedings of the First international conference on High Performance Computing and Communications
Year:
2005

Citing 3
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VLSI array processors

VLSI array processors
Low-Energy Digit-Serial/Parallel Finite Field Multipliers

Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
Elliptic curves in cryptography

Elliptic curves in cryptography

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Abstract

This paper presents a new digit-serial systolic multiplier over GF(2m) for cryptographic applications. The proposed array is based on the most significant digit first (MSD-first) multiplication algorithm. Since the inner structure of the proposed multiplier is tree-type, critical path increases logarithmically proportional to D, where D is the selected digit size. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementations.