VLSI array processors
A systolic array design methodology for sequential loop algorithms
A systolic array design methodology for sequential loop algorithms
Bit-level systolic arrays for finite-field multiplications
Journal of VLSI Signal Processing Systems
Principles of digital design
New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)
IEEE Transactions on Computers
A method for obtaining digital signatures and public-key cryptosystems
Communications of the ACM
Elliptic Curve Public Key Cryptosystems
Elliptic Curve Public Key Cryptosystems
A Systolic Power-Sum Circuit for GF(2/sup m/)
IEEE Transactions on Computers
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The current paper presents a new algorithm and two architectures for the power-sum operation (AB2 + C) over GF(2m) using a standard basis. The proposed algorithm is based on the MSB-first scheme and the proposed architectures have a low hardware complexity and small latency compared to conventional approaches. In particular, the hardware complexity and latency of the proposed parallel-in parallel-out array are about 19.8% and 25% lower, respectively, than Wei's. In addition, since the proposed architectures incorporate simplicity, regularity, modularity, and pipelinability, they are well suited to VLSI implementation and can be easily applied to inverse/division architecture.