Low Complexity Bit Serial Systolic Multipliers over GF(2m) for Three Classes of Finite Fields

Authors:
Soonhak Kwon
Affiliations:
-
Venue:
ICICS '02 Proceedings of the 4th International Conference on Information and Communications Security
Year:
2002

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Abstract

By using a standard polynomial basis, we present a low complexity bit serial systolic multiplier over GF(2m) when there exist the following types of irreducible polynomials, xm+xm-1+1, xm+驴i=0m-2 xi and 驴i=0m xi, an all one polynomial. When compared with most of other bit serial systolic multipliers, our multiplier needs two latches fewer in each basic cell. Therefore, the hardware complexity of our systolic array is approximately 20 percent reduced from other existing multipliers.