A New Hardware Architecture for Operations in GF(2m)

  • Authors:
  • Chang Han Kim;Sangho Oh;Jongin Lim

  • Affiliations:
  • -;-;-

  • Venue:
  • IEEE Transactions on Computers
  • Year:
  • 2002

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Abstract

The efficient computation of the arithmetic operations in finite fields is closely related to the particular ways in which the field elements are presented. The common field representations are a polynomial basis representation and a normal basis representation. In this paper, we introduce a nonconventional basis present a new bit-parallel multiplier which is as efficient as the modified Massey-Omura multiplier the type I optimal normal basis.