Implementing elliptic curve cryptography
Implementing elliptic curve cryptography
A New Hardware Architecture for Operations in GF(2m)
IEEE Transactions on Computers
How Secure Are Elliptic Curves over Composite Extension Fields?
EUROCRYPT '01 Proceedings of the International Conference on the Theory and Application of Cryptographic Techniques: Advances in Cryptology
Elliptic Scalar Multiplication Using Point Halving
ASIACRYPT '99 Proceedings of the International Conference on the Theory and Applications of Cryptology and Information Security: Advances in Cryptology
Fast Key Exchange with Elliptic Curve Systems
CRYPTO '95 Proceedings of the 15th Annual International Cryptology Conference on Advances in Cryptology
Communication-Computation Trade-off in Executing ECDSA in a Contactless Smartcard
Designs, Codes and Cryptography
Generic GF(2m) arithmetic in software and its application to ECC
ACISP'03 Proceedings of the 8th Australasian conference on Information security and privacy
An ECDSA pocessor for RFID athentication
RFIDSec'10 Proceedings of the 6th international conference on Radio frequency identification: security and privacy issues
Low power elliptic curve cryptography
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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We present a VHDL design that incorporates optimizations intended to provide digital signature generation with as little power, space, and time as possible. These three primary objectives of power, size, and speed must be balanced along with other important goals, including flexibility of the hardware and ease of use. The highest-level function offered by our hardware design is Elliptic Curve Optimal El Gamal digital signature generation. Our parameters are defined over the finite field GF(2178), which gives security that is roughly equivalent to that provided by 1500-bit RSA signatures.Our optimizations include using the point-halving algorithm for elliptic curves, field towers to speed up the finite field arithmetic in general, and further enhancements of basic finite field arithmetic operations. The result is a synthesized VHDL digital signature design (using a CMOS 0.5碌m, 5V, 25掳C library) of 191,000 gates that generates a signature in 4.4 ms at 20 MHz.