A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases

Authors:
Arash Reyhani-Masoleh
Affiliations:
Department of Electrical and Computer Engineering, The University of Western Ontario, London, Canada
Venue:
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Year:
2008

Citing 9
Cited 0

VLSI Architectures for Computing Multiplications and Inverses in GF(2m)

IEEE Transactions on Computers
Use of elliptic curves in cryptography

Lecture notes in computer sciences; 218 on Advances in cryptology---CRYPTO 85
Mastrovito Multiplier for All Trinomials

IEEE Transactions on Computers
Mastrovito Multiplier for General Irreducible Polynomials

IEEE Transactions on Computers
Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials

IEEE Transactions on Computers
Bit-Parallel Finite Field Multiplier and Squarer Using Polynomial Basis

IEEE Transactions on Computers
VLSI Designs for Multiplication over Finite Fields GF (2m)

AAECC-6 Proceedings of the 6th International Conference, on Applied Algebra, Algebraic Algorithms and Error-Correcting Codes
Guide to Elliptic Curve Cryptography

Guide to Elliptic Curve Cryptography
Parallel Multipliers Based on Special Irreducible Pentanomials

IEEE Transactions on Computers

Quantified Score

Hi-index	0.00

Visualization

Abstract

Multiplication is the main finite field arithmetic operation in elliptic curve cryptography and its bit-serial hardware implementation is attractive in resource constrained environments such as smart cards, where the chip area is limited. In this paper, a new serial-output bit-serial multiplier using polynomial bases over binary extension fields is proposed. It generates a bit of the multiplication in each clock cycle with the latency of one cycle. To the best of our knowledge, this is the first time that such a serial-output bit-serial multiplier architecture using polynomial bases for general irreducible polynomials is proposed.