Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
IEEE Transactions on Computers
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This paper describes a working implementation of astreaming encryption system for optical networks. The10 Gbps data stream is encrypted on the physical levelin both the wavelength and time domains. Security isobtained by applying a strong pseudo-random hoppingpattern to both. The AES algorithm in counter mode isused to control the switches that implement the hoppingpermutations. Because of the high throughputrequirements, aggressive parallelizing and pipeliningtechniques are used to achieve data rates of 10 Gbps.The core logic of the system was implemented on theVirtex2-XC2V1000 FPGA. Using four FPGA boardsand four serializer and deserializer chips, a secureswitch of 4 users over 4 wavelengths can be realized,resulting in a total throughput of 10 Gbps. This systemis important as a platform for further research in thearea of secure optical networks.