CryptoManiac: a fast flexible architecture for secure communication
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
FUNDAMENTAL DESIGN PROBLEMS OF DISTRIBUTED SYSTEMS FOR THE HARD-REAL-TIME ENVIRONMENT
FUNDAMENTAL DESIGN PROBLEMS OF DISTRIBUTED SYSTEMS FOR THE HARD-REAL-TIME ENVIRONMENT
The Non-preemptive Scheduling of Periodic Tasks upon Multiprocessors
Real-Time Systems
Area-Throughput Trade-Offs for Fully Pipelined 30 to 70 Gbits/s AES Processors
IEEE Transactions on Computers
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
New Schedulability Test Conditions for Non-preemptive Scheduling on Multiprocessor Platforms
RTSS '08 Proceedings of the 2008 Real-Time Systems Symposium
Celator: A Multi-algorithm Cryptographic Co-processor
RECONFIG '08 Proceedings of the 2008 International Conference on Reconfigurable Computing and FPGAs
CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
A reconfigurable crypto sub system for the software communication architecture
MILCOM'09 Proceedings of the 28th IEEE conference on Military communications
High-speed pipelined hardware architecture for Galois counter mode
ISC'07 Proceedings of the 10th international conference on Information Security
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This paper deals with the architecture, the performances and the scalability of a reconfigurable Multi-Core Crypto-Processor (MCCP) especially designed to secure multi-channel and multi-standard communication systems. A classical mono-core approach either provides limited throughput or does not allow simple management of multistandard streams. In contrast, parallel architecture of the MCCP provides either high encryption data rate or simultaneous use of different ciphers. Up to eight cores can be used at the same time to reach a maximum throughput of 3460 Mbps. Moreover, our architecture targets FPGA platforms to enable its evolution over the time by using hardware reconfiguration.