A fully pipelined memoryless 17.8 Gbps AES-128 encryptor
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
IEEE Transactions on Computers
Parallel Montgomery Multiplication in GF (2^k) Using Trinomial Residue Arithmetic
ARITH '05 Proceedings of the 17th IEEE Symposium on Computer Arithmetic
A New Approach to Subquadratic Space Complexity Parallel Multipliers for Extended Binary Fields
IEEE Transactions on Computers
Multi-gigabit GCM-AES Architecture Optimized for FPGAs
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Implementation of the AES-128 on virtex-5 FPGAs
AFRICACRYPT'08 Proceedings of the Cryptology in Africa 1st international conference on Progress in cryptology
AES on FPGA from the fastest to the smallest
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
High-speed pipelined hardware architecture for Galois counter mode
ISC'07 Proceedings of the 10th international conference on Information Security
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This work presents a new method to compute the GHASH function involved in the Galois/Counter Mode of operation for block ciphers. If X = X1 . . . Xn is a bit string made of n blocks of 128 bits each, then the GHASH function effectively computes X1Hn+X2Hn-1+ . . . XnH, where H is an element of the binary field F2128. This operation is usually computed by using n successive multiply-add operations over F2128. In this work, we propose a method to replace all but a fixed number of those multiplications by additions on the field. This is achieved by using the characteristic polynomial of H. We present both how to use this polynomial to speed up the GHASH function and how to efficiently compute it for each session that uses a new H.