HCH: a new tweakable enciphering scheme using the hash-encrypt-hash approach
INDOCRYPT'06 Proceedings of the 7th international conference on Cryptology in India
HCTR: a variable-input-length enciphering mode
CISC'05 Proceedings of the First SKLOIS conference on Information Security and Cryptology
A new mode of encryption providing a tweakable strong pseudo-random permutation
FSE'06 Proceedings of the 13th international conference on Fast Software Encryption
AES on FPGA from the fastest to the smallest
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
EME*: extending EME to handle arbitrary-length messages with associated data
INDOCRYPT'04 Proceedings of the 5th international conference on Cryptology in India
An Improved Security Bound for HCTR
Fast Software Encryption
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We present optimized FPGA implementations of three tweak-able enciphering schemes, namely, HCH, HCTR and EME using AES-128 as the underlying block cipher.We report performance timings and hardware resources occupied by these three modes when using a fully pipelined AES core and a sequential AES design. Our experimental results suggest that in terms of area HCTR, HCH and HCHfp (a variant of HCH) require more area than EME. However, HCTR performs the best in terms of speed followed by HCHfp, EME and HCH.