A High-Throughput Low-Power AES Cipher for Network Applications

Authors:
Shin-Yi Lin; Chih-Tsun Huang
Affiliations:
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu;-
Venue:
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Year:
2007

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Abstract

We propose a full-featured high-throughput low-power AES cipher which is suitable for widespread network applications. Different modes of operation are implemented, i.e., the ECB, CBC, CTR and CCM modes. Our cipher utilizes a cost-efficient two-stage pipeline for the CCM mode by a single datapath. With the design-for-test circuitry, the maximum throughput is 4.27 Gbps using a 0.13mum CMOS technology with a 333MHz clock rate. The hardware cost is 86.2K gates with the power of 40.9mW.